Hybrid Rule-based and Machine Learning System for Assertion Generation from Natural Language Specifications

We propose a hybrid approach for automatic generation of System Verilog assertions from natural-language specifications by combining machine-learning and formal analysis of the input text. The formal analysis focuses on parsing the input text, while the machine learning engine focuses on translating the input text to formal logic and/or assertions. Such a hybrid reduces the burden of a purely machine-learning based translation and increases accuracy in the generated assertions, especially for those complex assertions. In addition, the proposed hybrid approach offers a novel method to validate the assertions generated, in which the results of different machine-learning models are used to determine the confidence of the hybrid approach.