平版印刷术
极紫外光刻
光学接近校正
进程窗口
薄脆饼
计算机科学
计算光刻
光刻
炸薯条
下一代光刻
临界尺寸
多重图案
电子工程
纳米技术
光学
材料科学
工程类
抵抗
物理
电子束光刻
电信
图层(电子)
出处
期刊:Journal of micro/nanopatterning, materials, and metrology
[SPIE - International Society for Optical Engineering]
日期:2021-08-31
卷期号:20 (03)
被引量:51
标识
DOI:10.1117/1.jmm.20.3.030901
摘要
In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.
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