An interface trap charge model for simulation of graphene-based synaptic field effect transistors

We propose a compact computational method based on the capacitance model for the efficient design of graphene-based synaptic field effect transistors (FETs), in which the hysteresis of conduction characteristics due to the channel–gate interface trap is used as synaptic plasticity. Using our method to calculate the conduction properties of graphene and armchair graphene nanoribbon (AGNR) superlattice FETs, it is shown that the AGNR can achieve an efficient conductance change rate Δw, which is approximately 7.4 times that of graphene. It was also found that Δw was the greatest when the gate oxide thickness was around 2–3 nm, which is near the limit of miniaturization. These results suggest that the proposed synaptic FETs are a promising approach to realize large scale integration chips for biological timescale computation.