Low-Power Lane Detection Unit With Sliding-Based Parallel Segment Detection Accelerator for FPGA

Recently, with the development of semiconductors and VLSI (Very Large Scale Integrated Circuit), the technology required for autonomous driving is rapidly developing. One of the technologies that cannot be left out is the lane detection function. Lane recognition requires a lot of data from the camera sensor. As a result, the data size increases, making it difficult to process on a lightweight embedded board. This paper proposes a sliding-based parallel segment image processing method to solve this problem. Most boards in autonomous vehicles are lightweight, so the technique has been designed to reduce computation and power consumption. After fetching the image’s pixel data, grayscale conversion, Gaussian smoothing, Sobel operator, non-maximum suppression, and hysteresis are performed in parallel. Lanes were detected by performing a Hough transform operation on an image for which edge detection was completed in parallel. Due to the nature of parallel processing, it is more effective when image input is continuous and numerous than single image processing. This algorithm is written in C language and VHDL (VHSIC Hardware Description Language) for two parts in the board, DE1-SoC, FPGA (Field Programmable Gate Array) and HPS (Hard Processor System. Due to the use of the C language and VHDL, parallel programming uses 3.1 times less time, twice as much memory and slightly more power than sequential programming. For hardware languages such as Verilog, the computation algorithms have been converted to a fixed point. When comparing HPS and FPGA, the FPGA consumed significantly fewer resources, with 18 times shorter run time, 50 times fewer clock cycles, 3 times less power, and 183 times less energy. This provides a substantial benefit.