A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE

This paper presents a 5GHz All-digital phase locked loop (ADPLL) using Digitally-controlled oscillator with NMOS shunt regulator. The key feature, NMOS array embedded parallel to the core ring oscillator, tracks the net resistor value of Digitally-controlled resistor (DCR). A buffer based on Emitter follower lowers the DC voltage of supply power and keep the AC voltage, Power supply noise (PSN), minimizing the static current flowing through NMOS array. This circuit is implemented in 40-nm CMOS technology, and no additional area to embed NMOS array is needed in existing ADPLL. The simulation result of proposed circuit shows that PSN has attenuated by 75.7% in core oscillator power compared to DCO supply power.