Design and Analysis of high speed low power CMOS comparator with charge distribution technique

Comparators are fundamental blocks in the architectures of analog to digital converters. Due to the requirement of low power and high speed converters, the dynamic comparators are the natural choice. Existing dynamic comparators have issues of higher power consumption and delay. To overcome these drawbacks, a low power dynamic comparator with charge distribution technique is proposed in this paper. The proposed comparator reduces the regeneration time delay with the reduction in the power consumption considerably. The proposed design and simulation is carried out in 180 nm CMOS technology. Results show reduced power consumption of 260 µW and delay of 220 ps with supply voltage of 1.8 V at 0.5 GHz of frequency.