高电子迁移率晶体管
宽禁带半导体
击穿电压
模式(计算机接口)
光电子学
材料科学
氮化镓
电压
物理
凝聚态物理
纳米技术
晶体管
计算机科学
量子力学
图层(电子)
操作系统
作者
Yijin Guo,Yuan Qin,Matthew Porter,Zineng Yang,Ming Xiao,Yifan Wang,D. Popa,Loizos Efthymiou,Chu Cheng,K. Y. Cheng,Ivan I. Kravchenko,Linbo Shao,Florin Udrea,Yuhao Zhang
摘要
High-voltage GaN high electron mobility transistors (HEMTs) have recently reached the 10 kV milestone; however, prior reports relied on unconventional epitaxial structures—such as multi-channel, Si delta-doping, or unintentional p-GaN doping—which pose challenges in the realization of enhancement-mode (E-mode) gate control. Here, we demonstrate a 10 kV E-mode GaN HEMT with a standard highly doped p-GaN gate. This p-GaN layer also forms a reduced-surface-field (RESURF) structure. By analyzing devices with varying RESURF thickness (tR), we identify the key physical mechanism that enables the breakdown voltage (BV) upscaling with device length. We find the BV upscaling is only viable when tR is below 21 nm and reaches peak effectiveness at a tR of 17 nm—deviating from predictions based on ideal polarization superjunction theory. This suggests the presence of donor trap states that balance the acceptors in p-GaN. Additionally, the low Mg doping near the p-GaN/AlGaN interface, naturally formed in epitaxial growth, relaxes the precision required for tR control to maintain charge balance. Under the optimal tR, we demonstrate a 10 kV GaN E-mode HEMT with a specific on-resistance (RON,SP) of 69 mΩ cm2, which is lower than the RON,SP of 10 kV SiC MOSFETs. We also test a 5 kV device under prolonged high-temperature reverse bias stress at 3 kV and 150 °C. The device shows minimal parametric shifts, manifesting electrical and thermal reliability of the underlying charge modulation. The findings offer valuable guidance for the design of multi-kilovolt GaN power HEMTs using industry-standard wafers.
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