Determining Stress in Metallic Conducting Layers of Microelectronics Devices Using High Resolution Electron Backscatter Diffraction and Finite Element Analysis

Abstract Delayed failure due to stress voiding is a concern with some aging microelectronics, as these voids can grow large enough to cause an open circuit. Local measurements of stress in the metallic layers are crucial to understanding and predicting this failure, but such measurements are complicated by the fact that exposing the aluminum conducting lines will relieve most of their stress. In this study, we instead mechanically thin the device substrate and measure distortions on the thinned surface using high resolution electron backscatter diffraction (HREBSD). These measurements are then related to the stresses in the metallic layers through elastic simulations. This study found that in legacy components that had no obvious voids, the stresses were comparable to the theoretical stresses at the time of manufacture (≈300 MPa). Distortion fields in the substrate were also determined around known voids, which may be directly compared to stress voiding models. The technique presented here for stress determination, HREBSD coupled with finite element analysis to infer subsurface stresses, is a valuable tool for assessing failure in layered microelectronics devices.