Novel Subthreshold Modelling of Advanced On-Chip Graphene Interconnect Using Numerical Method Analysis

In VLSI integrated circuits, devices and interconnects are the steady pillars for designing and realization of the entire system. Demand for ultra-low power requirements has become very essential in today’s modern portable and miniaturized electronic gadgets. The subthreshold modelling and its utility for miniaturized gadgets and low power applications have increased tremendously in recent days. Operating devices and interconnects in the subthreshold region profoundly enhance the performance of the system. In this paper, contemporary subthreshold modelling has been energetically taken. The novel modelling of subthreshold for device and on-chip interconnects has been first time presented using the numerical method based finite-difference time-domain (FDTD) technique. The advanced graphene on-chip interconnects have been considered for the performance analysis. The technology node considered is 22 nm. It is analysed that graphene-based MLGNR interconnects possess better performance over copper interconnects. It is also seen that subthreshold region of operation leads to significantly lower power dissipation than in linear region. Power saving with the subthreshold region of operation in case of conventional copper and advanced graphene interconnects is nearly 22% and 26% respectively. The veracious proposed FDTD modelling for the subthreshold region is highly accurate with respect to SPICE simulation results. The average percentage error for transient simulation is less than 2%.