放大器
电气工程
拓扑(电路)
基带
噪音(视频)
物理
滤波器(信号处理)
前端和后端
计算机科学
CMOS芯片
电子工程
工程类
人工智能
操作系统
图像(数学)
作者
Jin Jin,Jianhui Wu,R. Castello,Danilo Manstretta
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2022-04-01
卷期号:57 (7): 1957-1967
被引量:4
标识
DOI:10.1109/jssc.2022.3161340
摘要
This work reports on a low-intermediate frequency (IF) voltage-mode receiver front-end for Internet-of-Things (IoT) applications. Design and noise analysis of an unbalanced gate-boosted common-gate low-noise amplifier (LNA) is presented, showing 50% lower power dissipation compared with the conventional balanced topology. Improved linearity is achieved thanks to channel-selection, consisting of two complex poles centered at 2 MHz IF. The first complex pole is embedded in the passive down-conversion mixer for improved frequency selectivity in front of the baseband voltage amplifier. Built in a 28-nm CMOS process, the proposed front-end occupies an active area of 0.175 mm 2 , it is supplied with 1 V and consumes only 400 $\mu \text{W}$ , while showing a minimum noise figure (NF) of 6.8 dB and an out-of-band (OOB) IIP 3 of −0.35 dBm. The performance meets Bluetooth low-energy (BLE) requirements and is competitive with other sub-mW receivers.
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