A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation

A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. To improve the accuracy of the common-mode feedback circuit and speed up the settling of the ring amplifier, an improved bias-enhanced ring amplifier is proposed. Additionally, to alleviate the loss of the ring amplifier's DC gain in the nanoscale CMOS process and to migrate the dynamic offset caused by the non-ideal switches, a gain error cancellation method is introduced by adding a feedforward amplification path. Designed in a 1 V 28 nm CMOS process, two cascaded pipeline stages and two time-interleaved SAR sub-ADCs make up the ADC. In the post layout simulation that includes transient noise and other non-ideal factors, this 12-bit ADC achieves 60.9dB SNDR and 72dB SFDR at a Nyquist input and sampled at 800 MS/s without analog cancellation, consuming 16.02mW. With gain error cancellation, SFDR is improved by more than 3dB.