材料科学
光电子学
栅极电介质
薄脆饼
击穿电压
电介质
晶体管
随时间变化的栅氧化层击穿
阻塞(统计)
制作
图层(电子)
栅氧化层
介电强度
电压
电气工程
纳米技术
计算机科学
工程类
医学
计算机网络
替代医学
病理
作者
Saptarshi Mandal,Anchal Agarwal,Elaheh Ahmadi,Mahadevabhat Kanathila,Matthew A. Laurent,S. Keller,Srabanti Chowdhury
摘要
In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.
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