A Study of Fault Coverage of Standard and Windowed Watchdog Timers

Both standard and windowed watchdog timers were designed to detect flow faults and ensure the safe operation of the systems they supervise. This paper studies the effect of transient failures on microprocessors, and utilizes two methods to compare the fault coverage of both watchdog timers. The first method is injecting a fault while a processor is reading an image from RAM and sending it to the VGA RAM for display. This method is implemented on FPGA, and visually demonstrates the existence of fast watchdog resets which can not be detected by standard watchdog timers, and faulty resets which occur undetected within the safe window of the windowed watchdog timers. The second method is a simulation where the fault coverage for each watchdog timer system is calculated. This simulation tries to take into consideration many factors which could affect the outcome of this comparison.