A PSRR-Enhanced Fast-Response Inverter-Based LDO for Mobile Devices

A low-dropout (LDO) regulator controlled by an inverter-based amplifier is proposed to accomplish the latest processor power requirements. The proposed inverter-based amplifier provides a high DC gain in low-voltage operation. Furthermore, an auxiliary non-inverting amplifier is adopted to regulate the wider output voltage and enhance power supply rejection ratio (PSRR) performance. The proposed LDO regulator has been implemented in a 28-nm CMOS process and provides an output range of 0.2-1.05 V from the input range of 0.4-1.1 V. With the input voltage of 1 V, the settling time is within 71.8 ns for 50-mV overshoot and 63 ns for 47-mV undershoot. With the low input voltage of 600 mV, the settling time is within 269 ns for 81-mV overshoot and 182 ns for 84-mV undershoot. The measured values of PSRR are 44.3 dB and 25.0 dB at 100 kHz and 10 MHz at 1-V input voltage, respectively. The PSRR with 600-mV input voltage shows 30 dB up to 600 kHz.