Design of transient enhanced output-capacitor-less flipped voltage follower based LDO regulator with a fast control loop for wide range of capacitive loads

A fast low dropout (LDO) regulator based on flipped voltage follower (FVF) with impedance compensation, is presented. This LDO offers stable regulation over wide range of load capacitances starting from 10 pF to 10 nF. It provides an extended load regulation from 100 μA to 30 mA. This enhancement is achieved by incorporating a voltage combiner stage along with an active feed-forward into the regulating loop. Unconditional stability for wide range of loads is ensured with the help of Miller’s compensation with a nulling resistor by the use of on-chip 75 pF capacitor, 4.5 kΩ MOSFET resistor and a feed forward capacitor. The proposed LDO is verified with simulation in 45 nm CMOS process. For an input voltage of a 1.2 V–2 V, LDO offers a regulated output of 1.07 V, with a minimal drop out voltage. Under a load transient of 100 μA to 30 mA within 1ns of edge time, the undershoot and overshoot are limited respectively to 35 mV and 82 mV, with almost 295 ps of response time. The quiescent current excluding the control voltage generator is 81–112 uA, which provides excellent current efficiency. The simulated PSRR is −42 dB over the band of 10 Hz–10 kHz, −20 dB at 1 MHz over 100 uA–50 mA of load currents also across varying load capacitors of 10 pF–10 nF. The line regulation is approximately 1.35mV/ V and load regulation is around 2 μV/mA.