Residual Stress and Warping Analysis of the Nano-Silver Pressureless Sintering Process in SiC Power Device Packaging

Chip bonding, an essential process in power semiconductor device packaging, commonly includes welding and nano-silver sintering. Currently, most of the research on chip bonding technology focuses on the thermal stress analysis of tin–lead solder and nano-silver pressure-assisted sintering, whereas research on the thermal stress analysis of the nano-silver pressureless sintering process is more limited. In this study, the pressureless sintering process of nano-silver was studied using finite element software, with nano-silver as an interconnect material. Using the control variable method, we analyzed the influences of sintering temperature, cooling rate, solder paste thickness, and solder paste area on the residual stress and warping deformation of power devices. In addition, orthogonal experiments were designed to optimize the parameters and determine the optimal combination of the process parameters. The results showed that the maximum residual stress of the module appeared on the connection surface between the power chip and the nano-silver solder paste layer. The module warping deformation was convex warping. The residual stress of the solder layer increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. With the increase in the coating area, it showed a wave change. Each parameter influenced the stress of the solder layer in this descending order: sintering temperature, cooling rate, solder paste area, and solder paste thickness. The residual stress of the nano-silver layer was 24.83 MPa under the optimal combination of the process parameters and was reduced by 29.38% compared with the original value of 35.162 MPa.