Bias‐Tunable Optoelectronic Synapse via a Graphene‐Gated Dual‐Gate Transistor

ABSTRACT This work presents a dual‐gate (DG) thin‐film transistor synapse that combines a transparent graphene top gate with type‐I InP/ZnS core–shell quantum dots to enable optically programmable, electrically erasable operation with high tunability. The transparent top gate preserves a vertical light path, allowing 405 nm illumination to write persistent photoconductance states, while a positive bottom‐gate pulse erases them. Compared with an otherwise identical Au‐gated control, the graphene‐gated device shows about two orders of magnitude higher electron mobility, lower off current, reduced hysteresis, and clean output saturation, forming a robust electrical baseline for opto‐synaptic functions. The DG structure provides an independent top‐gate bias knob, which sets postsynaptic current gain, paired‐pulse facilitation amplitude and time‐scale selectivity, and the linearity/symmetry of potentiation‐depression (P‐D) weight updates. Device‐informed simulations using a three‐layer artificial neural network demonstrate recognition accuracies up to ∼95% on the 28 × 28 handwritten‐digit task, with a clear operating window where update range and P‐D linearity are jointly optimized. This work provides a practical path to scalable, vision‐centric artificial neuromorphic device in which optical writing and electrical erasing are co‐designed with DG bias control.