异质结
薄脆饼
材料科学
原子单位
图层(电子)
光电子学
原子层沉积
薄膜
晶体管
薄膜晶体管
原子层外延
原子力显微镜
纳米技术
物理
量子力学
电压
作者
Pukun Tan,Chang Niu,Zehao Lin,Jian-Yu Lin,Linjia Long,Yizhi Zhang,G. D. Wilk,Haiyan Wang,Peide D. Ye
出处
期刊:Nano Letters
[American Chemical Society]
日期:2024-10-01
被引量:3
标识
DOI:10.1021/acs.nanolett.4c02969
摘要
There is an increasing demand for p-type semiconductors with scalable growth, excellent device performance, and back-end-of-line (BEOL) compatibility. Recently, tellurium (Te) has emerged as a promising candidate due to its appealing electrical properties and potential low-temperature production. So far, nearly all of the scalable production and integration of Te with complementary metal oxide semiconductor (CMOS) technology have been based on physical vapor deposition. Here we demonstrate wafer-scale atomic layer-deposited (ALD) TeO
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