Warpage optimization of memory-computing integrated chiplets with 2.5D packaging subjected to electrical-thermal-vibration multistress coupling

Purpose This study aims to minimize the warpage issue in memory-computing integrated chiplets with 2.5D packaging on a large-scale wafer subjected to multistress through synergistic optimization of key structure paraeters. Design/methodology/approach In this study, memory-computing integrated chiplet-based 2.5D packaging was designed and the warpage optimization under electro-thermal-vibration coupling was conducted with finite element analysis simulation. Compared studies were also conducted with the imposing condition of single electrical and thermal stress. Findings The research results indicated that electrical and thermal stress had a significant impact on the packaging warpage while that of vibration on warpage was minimal. For structure parameters, the chiplet thickness had a significant effect on the warpage of the model, while the influence of chiplet size was relatively small. When the chiplet thickness decreased to 100 µm, the warpage was reduced by 8.96%. Under thermal stress loading, the impact of packaging density on the overall warpage of the chiplet-based 2.5D packaging model is relatively small. However, under the loading of electrical stress or electro-thermal coupling, the packaging density has a severe impact on warpage, with the maximum approaching 1.3011 µm for just one chiplet. Compared with vibration alone, electro-thermal-vibration coupling slightly increased the warpage, which is primarily evident in the exacerbation of warpage in stacked chiplets and edge locations. Lower packaging density with 150 µm chiplet thickness contributed to a minimal warpage in stacked chiplet, the edge locations of which exhibited a relatively severe warpage. Research limitations/implications The research provides a theoretical basis for warpage optimization of memory-computing integrated chiplets with 2.5D packaging subjected to multistress coupling. Practical implications When designing the layout of chips for large-sized high-reliability silicon substrates, this method can be used to control the most severely warped areas at the edges, thus making it easier to optimize warpage. Originality/value With the approaching of physical limits dictated by Moore’s Law, advanced packaging technologies, primarily centered around 2.5D packaging and three-dimensional packaging, were attached importance to. It can integrated multifunctional chips, which have become increasingly complex, leading to greater difficulty in design and implementation, and an obvious increase in overall manufacturing costs. In this context, chiplets offered a viable approach for future chip designs. With the high demand for high-performance computing, memory-computing integrated chiplets were designed. The warpage of 2.5D packaging by altering structural parameters under multiphysical field coupling conditions was studied to provide a theoretical basis for warpage optimization of memory-computing integrated chiplets with 2.5D packaging.