Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts

Parasitic effects are extremely significant for the performance of analog and RF integrated circuits. Although layout retargeting for technology migration or specification update is able to preserve designers' intent, the associated layout parasitics cannot be guaranteed to meet the performance requirements. In this paper, we present a novel algorithm that performs parasitic-aware automatic layout retargeting for analog/RF integrated circuits. Given parasitic resistance/capacitance bounds and matching constraints ensuring desired circuit performance, the algorithm creates a reduced-template-graph from original layouts and adds parasitic constraints. Using a two-dimensional hybrid scheme of graph-based optimization and nonlinear programming, the nonlinear problem is solved effectively and efficiently. The algorithm has successfully retargeted operational amplifiers and an RF low-noise amplifier within minutes of CPU time.