Design of a 16-bit 500-MS/s SAR-ADC for low-power application

Nowadays, digital system technology is growing continuously, so the need of converting real-time (analog) data to digital data plays an important role. Whereas with the advancement in integrated circuit technology, the main concern of a designer is on power consumption. In digital systems, the key line among the real-time world to the digital era is the analog-to-digital converter (ADC). Some of its applications where ADC is a prominent block are healthcare and medical, traffic control, environmental monitoring, temperature monitoring, industrial control, and home automation. Among the numerous ADC architectures, one of the most efficient architectures that provides good energy consumption and can be used at low power is the successive approximation register (SAR). SAR-type analog-digital converter architecture is simple, and it is widely used due to low consumption of power, moderate speed with high resolution, and operated at the low-frequency band. These find a unique application in medical instruments and are operated at ultra-low power. Some of the biomedical devices where the SAR-ADC can be used are pacemaker, blood glucose monitor, electroencephalogram, electrocardiogram, and electromyogram, where amplitude ranges from 10 μV–100 mV for the applied bioelectric signals. This paper presents a design of 16-bit SAR-ADC for enhancing the conversion speed by using a comparator. For further improvement in the conversion speed of SAR logic, we will use an R-2R type digital-to-analog converter (DAC) due to its optimized power, less design complexity, greater accuracy, and providing improved matching. The proposed SAR-ADC can be designed using a sampling rate of 500 MS/s, and implementation of a circuit can be carried out on 45-nm CMOS technology, which will occupy an approximate area of 0.45 mm2 and thus produce a low power consumption that can be used for biomedical and other applications that require very low power to operate the device.