Performance comparison of ONOFIC and LECTOR based approaches for Leakage Power Reduction

Advancement in technology leads to the creation of more complex electronic devices which results in the minimization of battery life. Therefore, the saving power of electronic devices is the major concern in modern-day scenarios. As the size of digital circuits goes on decreasing, the problem of increasing leakage current is preventing us to design low power circuits. In this paper, different approaches for leakage power reduction in digital CMOS circuits are discussed. To reduce leakage power, LECTOR and ONOFIC techniques are used in various digital circuits like buffer, multiplexer, and flip-flop. Digital circuits have been implemented for high performance with optimized transistor sizing which is done based on Logical Effort Theory (LE theory). A comparative study of leakage power, delay, and leakage power-delay product (PDP) for the above-mentioned circuits is performed. The simulations of circuits are performed in LtSpice using 65nm PTM technology at a power supply of 0.9V.