A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop

This paper presents an integer-N sub-sampling phase-locked loop (SSPLL), which proposes a novel TDC-based frequency-locked loop (FLL) to fast lock the output frequency. This SSPLL is fabricated in a 90-nm CMOS. With a 40-MHz reference input, the measured RMS jitter (10 kHz–100 MHz) at 2.4 GHz is 495.7 fs while the reference spur is −63.8 dBc. The total power consumption is 4.41 mW. The proposed FLL achieves the average frequency-locking time of about 160 ns only when simulated across various PVT settings and re-locking conditions.