Extremely Low Thermal Resistance of β-Ga 2 O 3 MOSFETs by Co-integrated Design of Substrate Engineering and Device Packaging

High Resolution Image Download MS PowerPoint Slide Gallium oxide (Ga 2 O 3 ) emerges as a promising ultrawide bandgap semiconductor, which is expected to surpass the performance of current wide bandgap materials, like GaN and SiC, in electronic devices. However, widespread application of Ga 2 O 3 is hindered by its extremely low thermal conductivity and lack of effective device-level thermal management strategies. In this work, Ga 2 O 3 metal–oxide–semiconductor field-effect transistors (MOSFETs) are fabricated by conducting co-integrated design of substrate engineering with layer transferring and device packaging. 3D Raman thermography is introduced as a novel method to analyze the temperature distribution within the device, which provides valuable insights into their thermal performances. A high-quality Ga 2 O 3 -SiC heterogeneous integrated material is successfully fabricated with an extremely low interface thermal resistance of 6.67 ± 2 m 2 ·K/GW. Compared to the homoepitaxial Ga 2 O 3 MOSFETs, the degradation of I on / I off in Ga 2 O 3 -SiC MOSFETs is decreased by 1.5 orders of magnitude, and that of R on is decreased by 31%, showing the great thermal stability of Ga 2 O 3 -SiC MOSFETs. With the additional device packaging, a significant one order-of-magnitude reduction in the thermal resistance of the Ga 2 O 3 -SiC MOSFET is achieved, reaching a record-low value of 4.45 K·mm/W in the reported Ga 2 O 3 MOSFETs. This work demonstrates an efficient strategy for device-level thermal management in next-generation Ga 2 O 3 power and RF applications.