A Novel 1/1.3-inch 50 Megapixel Three-wafer-stacked CMOS Image Sensor with DNN Circuit for Edge Processing

This study reports the first ever 3-wafer-stacked CMOS image sensor comprising an artificial intelligence (AI) chip with a deep neural network (DNN)-based circuit. The sensor was fabricated by bonding wafer with a DNN-based circuit to the bottom of a conventional 2-layer-stacked image sensor comprising a pixel array on the top wafer and a sensor logic and an analog-to-digital converter on the middle wafer using the wafer-on-wafer-on-wafer process. This process allowed the sensor to retain excellent imaging characteristics without affecting those of the top and middle wafers. Additionally, considering the heat generation during operation is crucial for designing the circuit of the 3-layer-stacked chip; therefore, the high-power circuit was placed in the bottom chip to ensure heat dissipation. This novel image sensor comprising a DNN can enhance the gate scale and incorporate the high dynamic range (HDR) function. Moreover, the pixel-array area can be expanded to approximately the same size as that of the chip to realize a resolution of 50 MP. Thus, the proposed sensor can perform DNN processing on higher resolution HDR image data than the conventional DNN-equipped 2-layer-stacked image sensor, resulting in remarkably improved image-recognition and high-performance edge processing with a single chip.