Analysis of Resistance Change Development Due to Voiding in Copper Interconnects Ended by A Through Silicon Via

The resistance change due to electromigration induced voiding in modern copper interconnects ended by a Through Silicon Via (TSV) is analyzed. It is shown that two different modes of resistance increase exist during the period of void growth under the TSV. Primarily responsible are imperfections at the TSV bottom introduced during the fabrication process. Consequently, the time to failure of such structures under electromigration stress is likely to follow a bimodal distribution. An analytical model is proposed to explain the resistance change development based on published experimental data and also on numerical simulations.