LDO comparison with new Push-Pulled Flipped Voltage Follower topology for transient response improvement

In this paper, a Push-Pulled Flipped Voltage Follower Low Dropout Regulator (FVF LDO) is proposed to enhance Load and Line regulations. Two other LDOs architectures are studied as comparison: a commonly used Folded Cascode (FC) LDO and a typical FVF LDO. The three circuits have been designed to comply with the same specifications: technology node (40nm CMOS process), regulated output voltage (1.2V), output capacitance (10nF), maximum load current (100mA) and quiescent current (0.4mA). Simulation results (Load, Line and PSR) verify that Load and Line regulations are significantly improved by the new topology.