Improving the electrical performances of InSe transistors by interface engineering

InSe has emerged as a promising candidate for next-generation electronics due to its predicted ultrahigh electrical performance. However, the efficacy of the InSe transistor in meeting application requirements is hindered due to its sensitivity to interfaces. In this study, we have achieved notable enhancement in the electrical performance of InSe transistors through interface engineering. We engineered an InSe/h-BN heterostructure, effectively suppressing dielectric layer-induced scattering. Additionally, we successfully established excellent metal–semiconductor contacts using graphene ribbons as a buffer layer. Through a methodical approach to interface engineering, our graphene/InSe/h-BN transistor demonstrates impressive on-state current, field-effect mobility, and on/off ratio at room temperature, reaching values as high as 1.1 mA/μm, 904 cm 2 ⋅V −1 ⋅s −1 , and >10 6 , respectively. Theoretical computations corroborate that the graphene/InSe heterostructure shows significant interlayer charge transfer and weak interlayer interaction, contributing to the enhanced performance of InSe transistors. This research offers a comprehensive strategy to elevate the electrical performance of InSe transistors, paving the way for their utilization in future electronic applications.