Line edge roughness analysis and simulation at advanced litho process

Line edge roughness is the deviation of a feature edge from its ideal shape and is defined as three times the standard deviation. The deviation from the average line width is defined as line width roughness. As feature sizes shrink with Moore's Law, critical dimension variations caused by roughness cannot be ignored. Variations in transistor gate length can result in transistor leakage, and large distributions in transistor gate length can lead to large variations in transistor speed. From a process standpoint, the presence of roughness renders it more challenging to attain precise process control during manufacturing. In the lithography process, LER and LWR depend on several parameters, such as critical dimension, pitch, photoresist and its processing, source mask optimizations, focus, energy, etc. Therefore, an in-depth understanding of the roughness mechanisms is important for improving roughness. This paper has studied the interdependencies through the utilization of simulation techniques, and correlated with the measured roughness, using different critical dimension and pitch patterns. In consequence, a roughness mechanism has been obtained. The simulation can also predict roughness changes at other conditions to improve it.