DC and RF Performance Optimization of Source Pocket Designed Hybrid-Dielectric Vertical Nanowire Tunnel-FET: Low Power Perspective

Abstract This article addresses a new source pocket designed hybrid-dielectric vertical nanowire tunnel-FET (SP-HD-VNW-TFET). The existence of a source pocket at the source and channel boundary is shown such that the potential barrier at the tunnel-junction is minimized which causes ON current to rise. This article studied a comparison between a SP-HD-VNW-TFET device and source pocket vertical nanowire tunnel field effect transistor (SP-VNW_TFET). Using a hetero/hybrid-dielectric material boosts the electric field, resulting in higher tunneling current (1.72×10-6 A/µm). The device has undergone detailed investigation of both DC and AC characteristics like On-current, Off-current, ION/IOFF, Subthreshold-swing, Vt, gm, fT, GWB, and TFP. Source Pocket engineering and Hybrid dielectric inclusion increase device properties, including on-current and subthreshold swing (SS). The device's electrical properties have been evaluated and compared using the Sentaurus TCAD Tool.