Analyzing Embedded Non-Volatile Memory and Technology Optimizations for In-Memory Computing

This article quantitatively analyzes the limitations to energy efficiency and compute density for in-memory computing (IMC) based on today’s embedded non-volatile memory (eNVM) technology and provides insights for future technology optimizations for IMC application. While eNVM technologies have drawn interest for IMC due to their recent integration in foundry CMOS technologies and their ability to achieve high memory densities, IMC operation derives its efficiency and throughput density advantages through a signal-to-noise ratio (SNR) tradeoff. This article shows that today’s CMOS-integrated eNVM presents technology parameters that make IMC SNR limited by the readout circuitry, substantially preventing the benefits of memory density to be exploited, and limiting eNVM-based IMC below the efficiency and throughput density of prevailing digital accelerators. This article develops parametric models for IMC energy based on the fundamental tradeoffs and evaluates practical demonstrations of a recently presented magnetoresistive random access memory (MRAM)-based IMC design and a newly presented resistive RAM (ReRAM)-based IMC design against this. This can help guide future technology optimization targets for eNVM in IMC applications.