An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS

As essential building blocks of sequential digital circuits, optimizing the power consumption of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper proposes an ultra-low power 25-transistor (29-T with reset function) true single-phase clocked (TSPC) flip-flop by eliminating all redundant charges and discharges. Floating nodes are compensated by transistor-level optimization, which also enables a fully static and contention-free FF circuit design. The proposed FF is implemented in 55 nm CMOS technology. Post-layout simulation results demonstrate that at a supply voltage of 0.6 V and 10% data activity, the proposed circuit consumes only 0.153 fJ/cycle.