High-Performance Dual-Gate Transistors Based on Aligned Carbon Nanotubes

Aligned carbon nanotubes (A-CNTs), with atomic-scale thickness and ultrahigh carrier mobility, hold promise for constructing future sub-1 nm node integrated circuits (ICs) with higher speed and lower power consumption. However, the fabricated A-CNT transistors often suffer from the disorder of high-density CNT, which degrade the off-characteristic deviating significantly from theoretical values. Introducing a dual-gate (DG) configuration can provide higher gate control efficiency compared to conventional single-gate (SG) transistors and is expected to enhance the overall performance of A-CNT transistors. However, the reported A-CNT dual-gate field-effect transistors (DG-FETs) still exhibit nonideal switching behavior, and systematic exploration and optimizations for constructing high-performance A-CNT DG structures have been lacking so far. In this work, we conducted a detailed study on the matching issues between the top-gate (TG) and bottom-gate (BG) stacks. By optimizing the gate metal materials and dielectric layer thickness, we enabled 20 nm channel A-CNT DG-FETs to achieve leading switching characteristics, including an on-state current density (I_on) of up to 1.47 mA/μm, a peak transconductance (G_m) of 2 mS/μm, a subthreshold slope (SS) as low as 83 mV/decade, and a current on/off ratio of 10⁶. This study provides critical experimental guidance for constructing outstanding A-CNT DG-FETs at advanced technology nodes to compete with cutting-edge silicon-based chips and is also valid for two-dimensional channels.