A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.