Impact of STI-induced stress, inverse narrow width effect, and statistical V/sub TH/ variations on leakage currents in 120 nm CMOS

Leakage currents in 120 nm CMOS technology are dependent on STI-induced stress (STIS), inverse narrow-width effect (INWE), and statistical threshold voltage variations. In this paper, we analyze the impact of these effects on the gate-width dependence of the device off-current density. A threshold voltage model is proposed to describe the observed off-current minimum. STIS dominates the device behavior for large gate widths while INWE determines the off-current for gate widths below 1 /spl mu/m. Statistical threshold voltage variations are relevant for minimum-sized devices.