Effect of Electrons Trapping/De-Trapping at P(VDF-TrFE)/SiO2 Interface in Metal/Ferroelectric/Oxide/Semiconductor Structure With Ultra-Thin SiO2 By Anodization

In this work, electrical characteristics of metal- ferroelectric-oxide-semiconductor (MFOS) and metal- ferroelectric-semiconductor (MFS) device structures are measured and compared. The experimental results show that the low-k interface effect and dielectric properties can be effectively improved by using a high-quality 2.5 nm SiO2 as a buffer layer between the ferroelectric and semiconductor. At the same time, peak currents can be found under positive bias voltage in these fabricated MFOS device. To further understand this phenomenon, we exploit and examine it by two specific methods. First, using the hysteresis measurement to compare the I-V characteristics with or with SiO2. In this experiment, the MFOS device shows an extremely large ratio of Ipeak/Ivalley (9.3 A/A) that is larger than the MFS device (1.32 A/A). Second, investigating the peak current ratio with the different thickness of poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) copolymer in the MFOS devices. With this method, the largest ratio of Ipeak/Ivalley happens in the 190 nm film thickness case. Based on these experimental verifications, these results present a strong correlation between peak current and oxygen vacancies. As a consequence, a mechanism of electrons trapping and de-trapping via oxygen vacancies can be proposed. Utilizing this mechanism, it is suggested that the heterostructure of P(VDF-TrFE)/SiO2/Si device structure could be applied in multilevel data storage.