An Area-Efficient HQC Accelerator With Unified Parallel Modules and Fine-Grained Scheduling

The Hamming quasicyclic (HQC) scheme has been selected by NIST for standardization in postquantum cryptography (PQC). The hardware implementations of HQC face challenges, including high latency, significant hardware overhead, and insufficient system-level scheduling optimization. To address these challenges, an area-efficient HQC hardware accelerator is proposed, in which the architecture of critical computational modules is optimized, and system-level scheduling is comprehensively enhanced. In particular, a unified and parallel sampling module (PSM) is first proposed. By incorporating only a small amount of detection logic, the sampling latency is significantly reduced. Moreover, the PSM supports both constant weight word (CWW) and fast nonbiased (FNB) modes. Subsequently, a novel, unified, four-way parallel polynomial arithmetic module (PPAM) is proposed. An innovative shared register bank design is proposed, which effectively reduces BRAM overhead. In addition, the PPAM supports both polynomial addition and multiplication modes. Finally, to address the challenge of insufficient system scheduling optimization, a fine-grained overlapped execution scheme (FGOES) is proposed, which further increases the execution overlap among modules and reduces the overall system latency. The proposed architecture is verified on an Xilinx Artix-7 field-programmable gate array (FPGA). Under the three NIST security levels, compared with state-of-the-art designs, the area-time product (ATP) is improved by$2.05\times $to$11.02\times $,$2.33\times $, and$2.25\times $, respectively.