绝缘体上的硅
外延
材料科学
光电子学
纳米技术
硅
图层(电子)
作者
Justine Lespiaux,Joël Kanyandekwe,Tanguy Marion,L. Saidi,V. Lapras,Alice Bond,Fabien Bringuier,Jérôme Richy,Alan Thouvard,Tim Biet,Emmanuel Nolot,Ludovic Couture,Laurent Brunet,Philippe Rodriguez,Eva Dos Reis,Nicolas Gauthier,Adrien Blot-Saby,Jean‐Michel Hartmann
出处
期刊:ECS transactions
[Institute of Physics]
日期:2024-09-27
卷期号:114 (2): 271-295
标识
DOI:10.1149/11402.0271ecst
摘要
We focus here on various Selective Epitaxial Growth (SEG) processes used during the manufacturing of advanced p-MOSFET devices: (i) 20 nm thick in-situ boron doped Si 0.7 Ge 0.3 layers grown at 650 °C, 20 Torr then capped with 5 nm of Si:B (at 730 °C, 20 Torr) for Raised Sources and Drains (RSDs) and (ii) 8 nm intrinsic SiGe layers grown at 650–700 °C, 20 Torr for channels. Those layers were grown with a heavily chlorinated chemistry to maintain full selectivity versus SiN hard-mask or SiCO sidewall spacers. The impact of diborane, germane and hydrochloric acid mass-flows on growth kinetics and doping were first of all quantified on blanket wafers. Epitaxial processes were optimized in terms of (i) doping and growth rates, which should be as high as possible while still having superior structural and electrical properties and (ii) selectivity against dielectrics. In a second part, we highlight some of difficulties encountered when switching to patterned substrates. The morphology, faceting and loading effects in such layers are discussed.
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