Straining Monolayer MoS 2 Transistor on a Flat and Rigid SiO 2 Substrate

Strain engineering has played a key role in modern silicon electronics since 90 nm technology. Achieving similar advances within two-dimensional (2D) semiconductors is essential for their lab-to-fab transition. However, adapting silicon-based strain techniques to 2D transistors presents significant challenges; hence, previous studies are largely based on using a flexible substrate or nanocurved substrate, intrinsically limiting the practical application of 2D circuits. Here, we report a new strain engineering approach for 2D transistors without relying on the substrate, hence realizing strained 2D transistors on a standard flat and rigid SiO₂ substrate. Importantly, the device strain could be directly visualized by the channel length change through a microscope rather than by previous indirect characterization methods, such as Raman or photoluminescence. Furthermore, an in situ electrical measurement is also conducted for the same MoS₂ transistor under different strain values, and the monolayer carrier mobility increases linearly with the applied tensional strain, reaching an enhancement factor of 118%.