Efficient layout design automation for multi‐chip SiC modules targeting small footprint and low parasitic

It is important to reduce both the size and parasitic of power modules when designing a layout. However, the layout design often relies on experience and was time-consuming. The problem is particularly prominent in silicon carbide (SiC) modules, which requires more parallel dye compared with silicon counterparts. In this study, an algorithm for multi-chip SiC module layout design automation is proposed, which combines genetic algorithm, candidate searching idea, parallel operation and simplified evaluation models for enhancing computational efficiency with reasonable accuracy. A 12-chip half bridge SiC module is studied to verify the feasibility of the proposed method. The results indicate the method is robust and efficient, and can generate optimal layouts with low parasitic inductance and resistance as well as small footprint. It is believed that the method is feasible to guide the automatic optimal layout design for multi-chip SiC modules, targeting small footprint and low parasitic.