A −245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS

In this paper, we present a temperature compensated semi-digital integer-N PLL realized in a standard 130 nm CMOS technology, which achieves 48 fs rms phase jitter and a FOM of −245 dB. The presented design improves the phase noise performance of previously presented semi-digital PLLs by replacing the ring oscillator VCO by a semi-digitally tuned LC-tank VCO. In contrast to mostly digital PLLs, the presented architecture uses simple linear analog circuitry, removing the need for non-linear bang-bang PFDs or high speed oversampled ΣΔ-modulators.