The Discussion of the Typical BEOL Design Rules from 3 nm to 2 nm Logic Process with EUV and High NA EUV Lithography

With the purpose to continuously improve the speed and density of chip operation, the size of the transistors and the spacing between the transistors have been shrinking, following what is called the Moore's law in the last 40 years. When the logic process node reaches 3 nm or smaller, the room for the improvement in FinFET architecture is no longer available. Complementary FET (CFET) structure has been proposed to continue the performance improvement through area reduction with the NMOS placed on top of the PMOS. In this paper, through the use of a self-developed simulation program, we study the typical design rule patterns of the back-end-of-line (BEOL) metal and via layers from 3 nm and 2 nm logic processes. From the development roadmap of transistors, it can be seen that the pitch of BEOL metal layer from 3 nm CFET is around 20~24 nm, which can be realized by 0.33 NA Extreme Ultra-Violet (EUV) lithography with double pattering scheme using self-aligned litho-etch-litho-etch (SALELE) process. Taking 40~48 nm as the anchoring pitch, in order to obtain enough process windows, we make detailed design rules for some typical 2D patterns (such as dense pattern, semi-dense pattern, isolated pattern, Tip-to- Tip (TtT) and Tip-to-Line (TtL) patterns, etc.), and we can also calculate the minimum area of isolated patterns. The pitch of BEOL metal layer from 2 nm FinFET is assumed to be 14~18 nm, for which we have done process window simulation under both 0.33 NA and 0.55 NA EUV processes. We will compare both exposure processes on exposure energy, exposure latitude, line width roughness, and defect density originated from photon absorption stochastics. We will present a study on both the process cost and performance for the 3 and 2 nm photo processes.