Improving the Device Performance of LDMOS Through the Optimization of Structure

Considerable effort has been put into the development of LDMOS. The main issue in the development of LDMOS is to obtain the best trade-off between specific on-resistance Rsp and BV. In this paper, the influence of key size on device performance is systematically studied based on 55nm platform. By optimizing key dimensions, Rsp and BV are balanced. The BV of LDMOS is greater than 50V, and the performance of Rsp reaches the advanced level in the industry.