Effect of Top-Gate Dielectric Deposition on the Performance of Indium Tin Oxide Transistors

We report ultrathin ( ${\sim }4$ nm) channel indium tin oxide (ITO) transistors, comparing different precursors for atomic layer deposition (ALD) of the Al2O3 top-gate dielectric, and analyze the role of dielectric deposition on transistor performance and gate bias stress stability. Water-based ALD leads to very negative threshold voltage ( ${V}_{\text {T}}$ ), with devices remaining in the on-state. In contrast, both ozone and O2-plasma precursors yield devices that can turn off, but ozone-based ALD devices have less negative ${V}_{\text {T}}$ shift at short channel lengths, and relatively more positive ${V}_{\text {T}}$ at all channel lengths. We achieve maximum drive current, ${I}_{\text {max}} \approx 260 \mu \text{A}/\mu \text{m}$ at ${V}_{\text {DS}}=$ 1 V, on/off current ratio of $10^{{10}}$ (limited by the instrument’s noise floor) for ${L} \approx 700$ nm ozone-Al2O3 top-gated transistors. Across multiple devices, the effective mobility is $\sim $ 42 cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ and contact resistance is $\sim 376 \Omega \cdot \mu \text{m}$ . The transistors also show good gate bias stability with normalized ${V}_{\text {T}}$ shift of +0.12 V(MV/cm) $^{-{1}}$ at gate stress field >3 MV/cm, a $\sim 3\times $ improvement vs. our previous reports of uncapped ITO transistors.