Comprehensive Analysis of Paralleled SiC MOSFETs Current Imbalance Under Asynchronous Gate Signals

Parallel-connected power device is an extensively applied solution in the industry to increase the current rating of the converter system. However, due to the undesired printed circuit board (PCB) layout or semiconductor fabrication tolerance, mismatched drain–source current, which speeds up the aging process of a certain device, can be introduced. The application of silicon carbide (SiC) devices aggravates this problem due to their higher switching speed. Asynchronous gate signal lag brought by the different driver chip propagation delay, gate loop parasitic inductance, or asynchronous pulse width modulation (PWM) signal is a major reason for transient current imbalance. The analysis of its impact on switching behavior is yet to be clarified. Specifically, the analytical trajectory model of parallel-connected devices has not been thoroughly studied. In this article, different types of current imbalance of parallel-connected SiC MOSFETs are analyzed. Via deriving the trajectory model of parallel-connected SiC MOSFETs in different conditions, the physical mechanism of device paralleling is revealed. The quantitative relationship among semiconductor electrical parameter and important performance indicators, such as switching energy loss and current stress, can be derived. It can provide a theoretical basis for the current sharing strategy and device long-term reliability enhancement. The experimental study is conducted to validate the proposed analytical model.