Signal integrity analysis and Peripheral Component Interconnect Express backplane link compliance assessment

Abstract This article presents research conducted on the backplane high‐speed Peripheral Component Interconnect Express version 4 (PCIe gen4) link between central processor root complex and the end‐point device in order to confirm its compliance. Signal integrity analysis was performed using a method that included channel segmentation, development of corner models for channel segments, full‐wave electromagnetic simulation utilizing the finite element method (FEM) and the creation of cascaded channel models, as well as determination of the worst‐case models for the channel. The results of this analysis were then used to modify the channel design in order to decrease insertion loss. Changes in the design included utilizing a very low loss dielectric for the backplane board, correcting the sizes of differential pairs and decreasing the via stubs. Frequency domain simulation of the modified channel design has shown a 25% decrease in insertion loss. The calculation of eye diagrams for the modified design has confirmed that the channel parameters meet the requirements for the PCIe gen4 standard.