Challenges with SOT-MRAM integration towards N5 node and beyond

Spin Orbit Torque (SOT) magnetic random-access memory (MRAM) offers the possibility to realize non-volatile ultra-high-speed technology. SOT-MRAM can also potentially reduce embedded memory footprint, which would inturn reduce silicon cost. However, there are certain challenges to overcome for SOT integration with logic. SOTMRAM needs a tall 'VIA' for the MTJ connection to the transistor. The height of this tall 'VIA' can vary from 60nm to 300nm for the N5 technology node. The VIA Critical Dimension (CD) depends upon metal width (30nm) which connects MTJ to read transistor. Thus, the aspect ratio needed for proper SOT integration is at least 10. This high aspect ratio is a major challenge for SOT integration, but it can be reduced (even down to 2) at the cost of SOT and MTJ stack integration complexity. On the other hand, keeping WL spacing constant and reducing WL width to facilitate increased MTJ connecting metal width (hence improve the AR for the same height) will increase the WL resistance. This WL resistance increment degrades WL delay as parasitic resistance is more problematic than capacitance at advanced nodes. In conclusion, while a tall VIA for SOT-MRAM has integration challenges due to the high VIA aspect ratio, mitigating this by means of wider VIA CD can potentially increase WL delay. Therefore, a comprehensive DTCO considering different bit-cells, SOT integration options and Memory performance is needed for SOT technology to be adopted at the most advanced technology nodes.