电迁移
材料科学
铜互连
随时间变化的栅氧化层击穿
原子层沉积
物理气相沉积
钴
电介质
图层(电子)
沉积(地质)
可靠性(半导体)
化学气相沉积
光电子学
铜
介电强度
复合材料
电子工程
薄膜
冶金
电气工程
纳米技术
栅极电介质
晶体管
电压
功率(物理)
古生物学
工程类
物理
生物
量子力学
沉积物
作者
Nicholas A. Lanzillo,K. Choi,C.-C. Yang,K. Motoyama,Huai Huang,K. Cheng,J. Maniscalco,O. van der Straten,C. Penny,T. Standaert
标识
DOI:10.1109/led.2019.2940869
摘要
We investigate the performance and reliability characteristics of Cu interconnects with Ta-based barrier layers and Co wetting layers at 7nm node dimensions with a focus on the impacts of reducing the Co thickness from 30Å down to 10Å. We demonstrate that while reducing Co liner thickness significantly reduces RC delay, there is a significant reduction in electromigration reliability below a thickness of 20Å if used in conjunction with a PVD (physical vapor deposition) TaN barrier. However, if the PVD treatment is followed by deposition of a thin ALD (atomic layer deposition) TaN, the Co layer thickness can be scaled down to 10Å without any penalty in either electromigration or time dependent dielectric breakdown (TDDB.) The combined PVD/ALD process with 10Å Co enables a 14% reduction in RC delay relative to our control split.
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