串行解串
收发机
均衡(音频)
模拟前端
均衡器
误码率
有效位数
多路复用器
电子工程
锁相环
奈奎斯特-香农抽样定理
计算机科学
电气工程
电信
多路复用
解码方法
相位噪声
工程类
CMOS芯片
频道(广播)
作者
Yoel Krupnik,Yevgeny Perelman,Itamar Levin,Yosi Sanhedrai,Roee Eitan,Ahmad Khairi,Yizhak Shifman,Yoni Landau,Udi Virobnik,Noam Dolev,Alon Meisler,Ariel Cohen
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2020-01-08
卷期号:55 (4): 1077-1085
被引量:59
标识
DOI:10.1109/jssc.2019.2959511
摘要
A 112-Gb/s PAM4 analog-to-digital converter (ADC)-based serializer/de-serializer transceiver (SERDES) receiver is implemented on Intel's 10-nm FinFET process. The receiver consists of a low-noise resonant analog front end (AFE) which provides equalization and gain at 28 GHz, a 64-way time-interleaved ADC, digital equalization consisting of a 16-tap feed-forward equalizer (FFE), and a 1-tap decision-feedback equalizer (DFE), as well as a clock and data recovery (CDR) loop utilizing a 7-GHz digitally controlled oscillator (DCO). Long-reach, -35 dB Nyquist channels are supported by a pre-forward error correction (FEC) bit error rate (BER) of 1e-6, thus making it compatible with existing and projected IEEE Ethernet specifications.
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