The effect of silicon anisotropy on the thermal stress of TSV structure of 3D packaging chip under thermal cyclic loads

Due to the existence of anisotropy, the previous isotropic assumption of silicon-based materials can no longer accurately characterize the mechanical behavior of materials. In this study, finite element analysis (FE A) method was adopted to research the effect of silicon anisotropy on the thermal stress of through silicon via (TSV) structure including copper pillar arrays in stacked 3D packaging chips under thermal cyclic loads. The simulation results show that, in both isotropic and anisotropic cases, the high thermal stress is always located at the interface between two materials in the structure. Compared to the isotropic case, the magnitude of thermal stress is always larger in the anisotropic case. In both isotropic and anisotropic cases, the maximum thermal stress in the bottom TSV copper column arrays is always slightly larger than that in the upper layer arrays, and the thermal stress of the copper column at the farthest diagonal line is most concentrated.